The present invention relates to IEEE Standard 1149.1 compliant ICs, and more particularly to IEEE Standard 1149.1 compliant PLDs.
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. Similar to CPLDs, the CLBs, IOBs and interconnect lines of FPGAs are controlled by configuration data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller ( less than 100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs has become harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDs, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
As the capacity and performance of PLDs continues to increase, so too does the complexity of the configuration data used to configure the PLDs. In many instances, the configuration data is developed and modified over a long period of time, and represents a significant investment to the company that develops the configuration data. To protect the proprietary interests of such companies, a security function is provided on most PLDs that prevents a would-be pirate from simply downloading the configuration data from the PLD, thereby preventing the would-be pirate from replicating or reproducing the circuit design implemented on the PLD. This security function is typically implemented as a programmable bit that is set during PLD configuration.
IEEE Standard 1149.1 defines circuitry that allows test instructions and associated test data to be fed into a compliant IC and, subsequently, allows the results of execution of such instructions to be read out of the compliant IC. All information (i.e., instructions, test data, and test results) is communicated in a serial format via a four pin serial interface (referred to as the Test Access Port, or TAP) that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine that facilitates loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. As set forth in greater detail below, one such task is a special instruction named INTEST. The INTEST instruction allows static (slow-speed) testing of the on-chip system logic, with each test pattern and response being shifted through a series of Boundary-Scan registers located, for example, at the I/O pins of IEEE Standard 1149.1 compliant PLDs.
A problem presented by IEEE Standard 1149.1 compliant PLDs is that the INTEST instruction can be used by potential pirates to thwart the security function of a PLD in order to replicate or reproduce the circuit design implemented on the PLD. This problem is set forth is additional detail below by first describing IEEE Standard 1149.1 circuitry found on compliant PLDs, and then illustrating by example how the INTEST instruction can be used to determine the configuration data stored on the PLD.
Originally, IEEE Standard 1149.1 was developed to test the interconnections and IC device placement on PCBs through connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, IEEE Standard 1149.1 has been extended to include device self-tests, diagnostics, and functional tests such as the INTEST instruction.
FIG. 1 shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB 100 and includes a first PLD 110 and a second PLD 120.
PCB 100 includes normal operation copper traces formed on a board of insulating material that provide signal paths between a PCB connector 101 and PLDs 110 and 120, and between PLDs 110 and 120. These normal operation copper traces are used, for example, to transmit configuration signals to PLDs 110 and 120, and to carry data signals during device operation. In addition to the normal operation copper traces, PCB 100 includes special purpose copper traces for transmitting signals associated with IEEE Standard 1149.1. These special purpose copper traces include a first trace 102 for transmitting test data-in (TDI) signals, a second trace 103 for transmitting test data-out (TDO) signals, a third trace 104 for transmitting test clock (TCK) signals, and a fourth trace 105 for transmitting test mode select (TMS) signals. Data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are transmitted on first trace 102 to first PLD 110, and pass through first PLD 110 along a line 144(1). TDO signals are transmitted from PLD 110 and received as TDI signals by second PLD 120 along a linking trace 106, and pass through second PLD 120 along a line 144(2). Finally, TDO signals are transmitted from PLD 120 to PCB connector 101 on second trace 103. In contrast to the data signals, each compliant device receives the TCK and TMS signals in a parallel manner.
Each PLD of an electronic system includes IOBs that configure the device terminals (pins) for transmitting signals to or from the PLDs programmable core logic circuitry. As shown in FIG. 1, first PLD 110 includes I/O terminals 112 that transmit/receive signals via lines 114 through respective IOBs 116 to/from programmable core logic circuit 118. Similarly, second PLD 120 includes I/O terminals 122 that transmit/receive signals via lines 124 through IOBs 126 to/from core logic circuit 128.
Unlike ASICs, the functions performed by both core logic circuit 118 and IOBs 116 of PLD 110 are determined by configuration data loaded after fabrication. That is, function or functions to be performed by the programmable interconnect and logic circuitry associated with a PLD is determined after fabrication. Similarly, the determination of which I/O pins will be used for input operations, and which I/O pins will be used for output operations is made after fabrication. As described in additional detail below, this flexible pin usage requires each IOB 116 to include programmable circuitry capable of performing both input and output operations.
In addition to core logic and input/output circuitry, each IC device that complies with IEEE Standard 1149.1 includes dedicated pins and hardware elements (referred to herein as Boundary-Scan architecture). Referring to FIG. 1, first PLD 110 includes four pins 142(1) through 142(4) that are respectively connected to trace 102 (TDI), trace 105 (TMS), trace 104 (TCK) and trace 106 (TDO). Similarly, second PLD 120 includes four pins 142(5) through 142(8) that are respectively connected to trace 106 (TDI), trace 104 (TCK), trace 105 (TMS) and trace 103 (TDO). The Boundary-Scan architecture of each PLD 110 and 120 includes control circuitry (TEST CONTROL CIRCUIT) and one or more data registers (not shown) that are, for example, incorporated into IOBs 116 and 126. The data and control circuitry of the Boundary-Scan architecture provided on each compliant device utilize the signals received on the four dedicated pins.
FIG. 2 is a detailed block diagram showing an example of the basic hardware elements associated with the Boundary-Scan architecture of an IEEE Standard 1149.1 compliant PLD. The basic hardware elements include a test access port (TAP) 210, a TAP controller 220, an instruction register (IR) 230, an instruction decode circuit 235, a test data register circuit 240, an output multiplexer (MUX) 250, an output flip-flop 260 and a tri-state buffer 270. These hardware elements are well known to those of ordinary skill in the art of designing IEEE Standard 1149.1 compliant ICs. Therefore, only basic hardware elements that are utilized to perform the INTEST instruction will be described herein.
TAP 210 provides access to the test support functions build into an IEEE Standard 1149.1 compliant PLD. TAP 210 includes three input connections for receiving the test clock input (TCK) signal, the test mode select (TMS) signal, and the test data input (TDI) signal. The TCK signal allows the Boundary-Scan architecture to operate synchronously and independently of the built-in system clock provided on the PLD. The TMS signal is used to control the state of TAP controller 220, as discussed below. The TDI signal is used for serial transmission of data or instruction bits, depending upon the state of TAP controller 220. TAP 210 may also include an optional fourth input terminal for receiving a test reset input signal for asynchronous resetting of TAP controller 220. In addition to the above-mentioned input connections, TAP 210 includes an output connection through which the TDO signals are transmitted. Depending upon the state of TAP controller 220, the TDO signal is used to serially shift either instruction register or data register contents out of the PLD.
FIG. 3 is a state diagram for explaining the operation of TAP controller 220 (shown in FIG. 2). The basic function of TAP controller 220 is to generate clock and control signals required for the correct sequence of operations of instruction register 230, test data register circuit 240, output MUX 250, output flip-flop 260 and tri-state buffer 270. Specifically, TAP controller 220 control signals that facilitate loading of instructions into instruction register 230, shifting TDI data into and TDO data out of the data registers in test data register circuit 240, and performing test actions such as capture, shift and update test data. These signals are provided in accordance with the state of TAP controller 220. All state transitions (indicated as arrows in FIG. 3) within TAP controller 220 occur in accordance with the serially received TMS values (shown next to each arrow).
FIG. 4 is a simplified schematic diagram showing an IOB 116 that includes a portion of the Boundary-Scan architecture formed along line 144(1) of first PLD 110 (see FIG. 1). IOB 116 includes an input buffer IB, a tri-state buffer TS and Boundary-Scan Register (BSR) cells 243(1) through 243(3). IOB 116 is configured by an output enable (OE) signal (which is transmitted through BSR cell 243(3)) either to receive input data signals applied to an I/O pin 112, or to transmit output data signals to I/O pin 112. When the OE signal is in a first state (e.g., low), IOB 116 is configured for receiving input signals from I/O pin 112 (i.e., tri-state buffer TS is set in a tri-state mode). In the input mode, input buffer IB transmits DATA IN signals applied to I/O pin 112 through BSR cell 243(1) and on a SYSTEM INPUT line to, for example, the PLD core logic circuit. Conversely, when the OE signal is in a second state (e.g., high), IOB 116 is configured for transmitting output signals to I/O pin 112. In the output mode, output signals transmitted on a SYSTEM OUTPUT line from, for example, the PLD core logic circuit are applied to I/O pin 112 through BSR cell 243(2) and tri-state buffer TS.
BSR cells 243(1) through 243(3) are linked in the manner described below to form a BSR chain along which test data bits are shifted to implement, for example, INTEST procedures. Each BSR cell 243(1) through 243(3) respectively includes an input multiplexer (MUX) 410(1) through 410(3), a shift register flip-flop 420(1) through 420(3), a parallel latch 430(1) through 430(3) and an output MUX 440(1) through 440(3). Each input MUX 410(1) through 410(3) is controlled by a SHIFT/LOAD-DR control signal to either load SYSTEM DATA or shift TDI data from a previous BSR cell of the BSR chain. The selected data is transmitted to shift register flip-flops 420(1) through 420(3) that store the received data in response to a CLOCK DR control signal generated by the TAP controller. Shift register flip-flops 420(1) through 420(3) transmit the stored data either to a next of the BSR cell (or to TDO if transmitted from the last BSR cell) and to parallel latches 430(1) through 430(3), respectively. Parallel latches 430(1) through 430(3) store the data from shift register flip-flops 420(1) through 420(3) in response to an UPDATE-DR control signal from the TAP controller, and transmit this data to output MUXes 440(1) through 440(3), respectively. Output MUXes 440(1) through 440(3) are controlled by a MODE TEST/NORM control signal from the instruction register to either transmit SYSTEM data (during normal operation) or the contents of parallel latches 430(1) through 430(3) (e.g., during INTEST procedures). The signals from output MUXes 440(1) through 440(3) are either transmitted to the core logic (when BSR cell 243 is associated with an input pin) or to the output pin of the PLD.
During INTEST procedures, test data signals are serially transmitted through BSR cells 243(1) through 243(3) in response to the SHIFT-DR and CLOCK-DR signals generated by the TAP controller. Specifically, BSR cell 243(1) receives a TDI signal from a previous BSR cell (not shown) of the BSR on line segment 144(A). This TDI signal is shifted through multiplexer 410(1) and shift register flip-flop 420(1) and transmitted to BSR cell 243(2). Subsequently, BSR cell 243(2) shifts this TDI signal through multiplexer 410(2) and shift register flip-flop 420(2), and transmits it to BSR cell 243(3). Finally, BSR cell 243(3) shifts the TDI signal through multiplexer 410(3) and shift register flip-flop 420(3), and transmits it on line segment 144(B) to a subsequent IOB associated with the BSR.
A problem associated with conventional IEEE Standard 1149.1 compliant PLDs supporting INTEST instructions arises because the Boundary-Scan architecture can be utilized to deduce the functionality of logic resident on the IC by shifting test data values into the BSR cells of IC on the BSR chain, and then analyzing the logic output generated in response to the entered values. By systematically entering all possible combinations of test data values into the BSR cells, the INTEST instruction provides an unintended path for the replication of the IC logic design that works around any device security feature. This problem is illustrated with reference to FIGS. 5(A) through 5(D).
FIGS. 5(A) through 5(D) are simplified schematic diagrams showing a conventional IEEE Standard 1149.1 compliant PLD 500 in which portions of programmable core logic circuit 518 are utilized to implement a two-input AND gate. PLD 500 includes three IOBs 116(1), 116(2) and 116(3), each including three BSR cells that are serially connected to form a BSR chain along line 505. IOBs 116(1), 116(2) and 116(3) are assigned to the input and output signals of the two-input AND gate implemented in core logic circuit 518. In particular, IOBs 116-1 and 116-2 are assigned to transmit input signals from their associated pins to the AND gate, and IOB 116-3 is assigned to transmit the output signal from the AND gate to its associated pin.
Referring to FIG. 5(A), at the beginning of the INTEST procedure, a series of test data values (1,0,0,0,0,1,1,0,0) are shifted into PLD 500 via the TDO terminal and BSR chain 505 from a test data source 510. The data shifting process is implemented by maintaining the TAP controller in SHIFT-DR state 305 (see FIG. 3) for the amount of time required to shift-in the test data values. Note that the test data values previously stored in IOBs 116(1), 116(2) and 116(3) (indicated with X) are simultaneously shifted along BSR chain 505 to test data source 510.
FIG. 5(B) illustrates the location of test data signals in IOBs 116(1), 116(2) and 116(3) after the shifting process is completed. In particular, a logic xe2x80x9c1xe2x80x9d is stored in BSR cells 243(11), 243(21) and 243(33), and a logic xe2x80x9c0xe2x80x9d is stored in the remaining BSR cells. At this point of the INTEST procedure, the TAP controller is moved into UPDATE-DR state 309 (see FIG. 3), thereby causing the test data values to be shifted from the shift register flip-flops 420(X) to the parallel latches 430(X) (see FIG. 4).
FIG. 5(C) illustrates the process of applying the test values in accordance with the internal logic of PLD 500. To perform this process, the TAP controller is moved to RUN-TEST/IDLE state 302, at which point the system clock of PLD 500 pulses to cause operation of core logic 518. As indicated by the arrows, the logic xe2x80x9c1xe2x80x9d values transmitted from BSR cells 243(11) and 243(21) are applied to the logic implemented in core logic 518, which generates an output value (i.e., logic xe2x80x9c1xe2x80x9d value) that is subsequently captured by BSR cell 243(32) when the TAP controller moved to CAPTURE-DR state 304 (see FIG. 3). Note that this logic xe2x80x9c1xe2x80x9d value overwrites any previously stored value.
Referring to FIG. 5(D), at the end of the INTEST procedure, a dummy series of test data values (X,X,X,X,X,X,X,X,X) are shifted into PLD 500 via the TDO terminal and BSR chain 505 from a test data source 510. The data shifting process is implemented by returning the TAP controller to SHIFT-DR state 305 (see FIG. 3). Note that the test data values stored in IOBs 116(1), 116(2) and 116(3) are simultaneously shifted along BSR chain 505 to test data source 510.
The test data values generated in FIG. 5(D) are then analyzed to determine the logic performed by PLD 500. By systematically transmitting sets of test data values and comparing the results, the logic implemented in core logic 518 can be replicated, thereby circumventing the IC logic design that works around any security feature provided on PLD 500.
What is needed is a Boundary-Scan architecture that includes a security device for selectively preventing INTEST operations after a IEEE Standard 1149.1 compliant PLD is configured, thereby preventing would-be pirates from replicating configuration data stored on the PLD.
The present invention is directed to a Boundary-Scan architecture for an IEEE Standard 1149.1 compliant IC that prevents would-be pirates from replicating the logic of the IC using INTEST or other Boundary-Scan instructions by blocking data that is shifted along the Boundary-Scan chain.
In accordance with the present invention, an IEEE Standard 1149.1 compliant IC includes a Boundary-Scan architecture having a security circuit including a switch controlled by a security bit that is selectively enabled or disabled by the IC programmer. In one embodiment, the switch includes a logic gate having a first input terminal and an output terminal connected directly to the Boundary-Scan Register (BSR) chain. The security bit applies a control signal to a second input terminal of the logic gate. When the security bit is in a first programmed state, the logic gate passes test data from the first input terminal to the output terminal that is shifted along the BSR chain to permit normal Boundary-Scan (e.g., INTEST) procedures. Conversely, when the security bit is in a second programmed state, the logic gate generates a predetermined data value onto the BSR chain despite the test data values received at the first input terminal (i.e., the shifted test data is blocked). Blocking the passage of shifted data prevents would-be pirates from using the INTEST operations to replicate the logic of the IC, or the logic function implemented by a PLD.
In another embodiment, the security circuit is located in a signal path connected between the I/O pin and the core logic circuit of a host PLD. During operation, the security circuit is selectively controlled to block test data values from being driven into or captured from the core logic circuit via an associated Boundary-Scan register (BSR cell). When the security bit of the security circuit is disabled, the security circuit passes the test data values being driven into or captured from the core logic circuit. In contrast, when the security bit of the security circuit is enabled, a high INTEST signal causes the security device to generate a low (logic xe2x80x9c0xe2x80x9d) output signal. This low output signal is captured by the associated BSR cell, and the transmitted along the BSR chain during a subsequent data shift operation. Consequently, instead of including test data indicating the configuration of the core logic circuit, the resulting data stream is entirely made up of low (logic xe2x80x9c0xe2x80x9d) output signals. Therefore, it is not possible for a would-be pirate to determine the logic implemented in core logic utilizing the INTEST instruction.